In a cache coherent network (CCN), hardware interfaces may be used to globally control power domains of all cache partitions in the network. This global approach is not feasible when a number of address domain regions are introduced, since each region will have its own power domain requirements. Moreover, interconnect implementations for a CCN that use hardware control for each cache partition becomes unmanageable at the System-on-Chip (SOC) level, as the number of cache partitions can be quite high.